1. Field of the Invention
The present invention relates to the field of integrated circuits.
2. Discussion of the Related Art
The fast development of technology has led to an increase in circuit complexity at the same time as a decrease in the commercial lifetime of circuits. Conversely, the time required by a manufacturing cycle (mask patterning, processing of the silicon wafers, circuit testing and encapsulating) remains significant.
Inevitably, after designing a complex integrated circuit, the first manufactured circuits frequently exhibit errors. The circuit can then be run back through the design steps to attempt to correct the error, prior to starting again a manufacturing batch. This requires a new thorough cycle of manufacturing, which is costly and long and can put the commercial interest of the circuit at risk.
It is thus often preferred to correct the hardware element formed by the integrated circuit itself. This, with the purpose of validating the correction on a few prototypes only. The correction on circuits produced in series can only be done by modifying the masks. An integrated circuit generally includes a semiconductor substrate currently made of silicon in which the several primary circuit components are formed. This substrate is topped by several levels of conductive layers (polysilicon, metallizations, generally called xe2x80x9cmetallization levelsxe2x80x9d). Once a defect has been identified in the integrated circuit, such as a missing logic function, high precision machines (MDL 1000 of Bertin/Spectra Physics for the laser cut, FIB (Focus Ion Beam) of Schlumberger for the cut and the perforation, the metal deposition and the oxide deposition) are used to perforate the metallization levels to obtain access to the terminals of the primary components, to disconnect these components and to connect back the inputs and the outputs of these components to a xe2x80x9cstandby cellxe2x80x9d in order to add the missing logic function.
Standby cells have no function in the circuit as long as this circuit does not require correction, and their inputs are conventionally grounded to avoid useless power consumption. Standby cells are conventionally implanted by groups. FIG. 1A schematically shows a conventional group 11 of standby cells formed of a NAND gate (1), of a D flip-flop (2) and of a tri-state gate (3) that enable a great variety of corrections.
FIG. 1B shows as an example a very simplified top view of an integrated circuit, the basic components of which have not been shown. In this integrated circuit 10, a great number of groups of standby cells 11 is implanted. These cells, in a repair, are to be connected to selected circuit nodes. These cells must be very numerous since a limitation of the above-mentioned correction method is that machines for establishing the replacement connections (conventionally by implantation of metal at the circuit surface) do not allow, for technical reasons, replacement connections to exceed a given length (xcex94). For a circuit to be possibly repaired at each of its nodes, each of its nodes must not be further than length xcex94 from a group of standby cells. Thus, standby cell groups 11 are conventionally arranged according to rows and columns distant by 2xcex94/{square root over ( )}2 from one another across the entire circuit 10 that is desired to be made repairable. Also, the groups of cells can be at a distance of xcex94/{square root over ( )}2 from the edges of the circuit that is desired to be made repairable. The standby cells, implanted among the basic circuit components, occupy a surface which is far from being negligible and increase the circuit surface, and thereby its cost.
Taking as an example a circuit such as shown in FIG. 1B, of 10 mmxc3x9710 mm, xcex94 being equal to 400 xcexcm, the number of implanted standby cell groups will be (10,000xc3x97{square root over ( )}2/400)xc3x97(10,000xc3x97{square root over ( )}2/400)=10,000/8=1,250. Assuming that a group of standby cells is formed of approximately forty transistors, the groups of standby cells in this embodiment according to prior art altogether amount to 1,250xc3x9740=50,000 transistors. A chip of 10 mmxc3x9710 mm conventionally amounts to one million transistors, and the standby cells represent in this case 5% of the chip surface, which will increase the chip price by at least 5%.
To maintain reasonable prices, there is a temptation to reduce the number of standby cell groups, and to place them only in the circuit areas which are the most likely to exhibit errors, but the insurance of being able to perform a repair at any node of the circuit is thereby lost, and problems of impossible repairs sometimes arise.
Another limitation of this method is associated with the fact that the cutting or the establishing of a connection leads to digging the upper surfaces of the circuit to the connection to be cut, and to the terminals of the standby cell which is desired to be connected. The deeper the elements to be reached, the more the subsequent digging operation and connection operation will be delicate, long and costly.
An object of the present invention is to overcome the disadvantages of the above-mentioned correction methods.
A more specific object of the present invention is to reduce the silicon surface occupied by the standby cells.
Another object of the present invention is to facilitate repair operations by reducing metallization layer crossing operations.
These objects as well as others are achieved by an integrated circuit including at least one group of standby cells connected to metal tracks arranged on the circuit so that any node of the circuit is distant from these tracks by at most the maximum value xcex94 allowed for an emergency repair. So connected, a single group of standby cells is sufficient to guarantee that at least one repair can be performed at any node of the circuit.
According to an embodiment of the present invention, the standby tracks are made in a single metal level as close as possible to the circuit surface, to facilitate a possible repair.
More specifically, the present invention provides an integrated circuit, at least one portion of which includes at least one group of standby cells for possible connection to said portion of the integrated circuit after manufacturing thereof by replacement connections, the length of which cannot exceed a predetermined value, and in which the inputs and outputs of the standby cells are connected to metal standby tracks being disposed oil the circuit such that any node of the circuit portion is distant by at most said predetermined value from any point the tracks.
According to an embodiment of the present invention, the circuit includes several metallization levels, and the standby tracks are mostly made in the highest possible metallization level.
According to an embodiment of the present invention, the inputs of a first group of standby cells are connected to a ground of the circuit and other groups of standby cells are connected in series with the first group by standby tracks arranged side by side in groups of standby tracks, so that no input of a standby cell is floating.
According to an embodiment of the present invention, the groups of standby cells are implanted substantially regularly along the groups of standby tracks.
According to an embodiment of the present invention, the groups of standby tracks are arranged in a zigzag pattern on the circuit portion in a succession of lines of same direction, extending across the entire width of the circuit portion, these lines being interconnected at each end by a portion of perpendicular column substantially equal to twice the predetermined value of a replacement connection.
According to an embodiment of the present invention, a group of standby cells is arranged substantially at one end of each line of a group of standby tracks.
According to an embodiment of the present invention, the inputs of the first group of standby cells are connected to the circuit ground by small segments of standby tracks.
According to an embodiment of the present invention, the outputs of a standby cell unconnected to a following standby cell are connected to small segments of standby tracks which have been left floating.
According to an embodiment of the present invention, a group of standby cells includes standard elements such as a NAND gate, a D flip-flop, and a tri-state gate.
The present invention also relates to a method comprising implanting in a portion of an integrated circuit at least one group of standby cells meant to be possibly connected to nodes of said integrated circuit portion after the manufacturing thereof by replacement connections, the length of which cannot exceed a predetermined value, and of connecting the inputs and outputs of the standby cells to metal tracks called standby tracks, being disposed on the circuit such that any node of said circuit portion is distant by at most said predetermined value from any point on these tracks, the standby tracks being made in the highest possible metallization level.
The foregoing objects, features and advantages of the present invention will be discussed in detail in the following non-limiting description of specific embodiments made in connection with the accompanying drawings.